For SRAM cells in general, static noise margin (SNM) and Vtrip are interdependent and design techniques that improve SNM, tend to degrade Vtrip and vice-versa. For example, the SNM can be improved by decreasing the voltage on the bitline, which weakens the passgate transistor. The SNM improves linearly with decreasing bitline voltage until the bitline voltage is about equal to the threshold voltage of the passgate transistor. In similar fashion, the voltage of the SRAM cell can be varied to improve the performance of the SRAM circuit.
These methods often involve using dual voltages for either read or write operations to improve cell margin. In most cases, a particular voltage is used in most operation states, but switching voltage when it is most advantageous. Implementation of a dual voltage SRAM circuit, requires providing a well regulated voltage for proper operation of the SRAM circuit and means to remove excess charge built up in SRAM circuit so the proper voltage can be maintained before the next operation state.
As a result, there is a need to solve the problems of the prior art to provide a method and apparatus for maintaining the proper voltage and removing excess charge built up in the SRAM circuit.